1. Field of the Invention
The present invention relates clock generators, and more particularly to a universal clock generator which is employed to selectively generate different clock rates for a plurality of different applications.
2. Description of the Related Art
Current circuit design typically employs a library of different circuit components. This library, which may be called a design library, is employed to select different prefabricated components needed to construct a circuit. A design library having many circuit components is often more difficult to search and incurs addition maintenance costs. It is therefore advantageous to reduce the number of the circuit components in the design library. Reducing the number of components also saves layout time and saves the library maintenance cost. In general, to simplify a circuit by reducing the number of circuit components is one goal of the designer. For example, in a 1 Gbit dynamic random access memory (DRAM) design, many ring oscillators are used to generate clocks with different oscillating frequencies. This provides for the implementation of different DC generators. For example, for a Vpp (or the boosted word-line voltage, e.g., 3.1V) active generator, a 30 MHz of clock is needed, for a Vbb (or the substrate bias voltage, e.g., xe2x88x920.5 V) active generator, a clock of 7 MHz is needed. For a generator to be used for a data path control, a clock of 5 MHz is needed, etc. Therefore, several oscillators are required in the Gb DRAM design to be used to generate different voltage levels. More clocks are also needed for other applications, for example, creating system timing, regulating refresh rate, etc.
It is time consuming to create each clock generator and individually trim each clock generator to provide a desirable oscillation rate for a specific application. Prior art devices include multiple clock frequency systems which are typically very complex and bulky. For example, in U.S. Pat. No. 4,977,581, a multiple clock system for multiple processor configurations is disclosed. A master clock system is used to synchronize sub-clock systems so that the multiple mainframe computers are capable of communicating with each other in real-time. This is the extension of the classic Phase Lock Loop (PLL) design. The PLL design has many variations, for example, U.S. Pat. No. 5,142,247. More detailed design theory and information on PLL""s can be found in the book entitled, Phase-Locked Loops Design, Simulation and Applications, by Roland E. Best, third edition, 1997.
Through digital or analog methods, a PLL circuit is able to generate a clock frequency that is an integer or fraction multiple of a reference frequency. The generated frequency has its phase synchronized with the reference frequency by using a charge pump and a voltage control oscillator (VCO). Although PLL designs tend to be very bulky, the PLL design is needed in conventional chip design for clock synchronization so that high-speed digital operation can be carried out in a parallel or pipe-lined manner. The PLL design is also localized. Clock signals generated from PLL are not easily sent to places on a chip where the signals may be needed.
Therefore, a need exists for a universal clock generator which can tailor the clock rate for different applications or usage. A further need exists for the universal clock generator to have a modular design to provide frequencies in a wide range using the same design, such that the layout, library maintenance, verification, simulation, etc. of the design are simplified. A still further need exists for a universal clock which can be customized at any location on a chip to service a specific application.
A universal clock generator circuit, in accordance with the present invention, includes an oscillator unit including circuitry for providing a first clock frequency. A plurality of load blocks are also included. The load blocks are selectively connectable to the oscillator such that a range of clock rates are derived from the first clock frequency by selectively connecting a number of the load blocks to the oscillator unit to provide one of a plurality of clock frequencies from a same output.
Another universal clock generator circuit, in accordance with the present invention, includes an oscillator unit including circuitry for providing a first clock frequency and a plurality of resistor blocks including resistive elements. The resistor blocks are selectively connectable to the oscillator. A capacitor block has at least one capacitor element which is selectively connectable to the oscillator unit. The plurality of resistor blocks and the capacitor block include selective connections which are enabled and disabled to adjust the first clock frequency by selectively connecting a number of the resistor blocks and capacitor elements to the oscillator unit to provide one of a plurality of clock frequencies from a same output.
In alternate embodiments, the oscillator may include a ring oscillator. The load blocks may include resistor blocks for adjustment of the one of a plurality of clock frequencies. The load blocks may include a plurality of groups of resistor blocks, and the groups of resistor blocks provide a plurality of levels of adjustment of the one of a plurality of clock frequencies. The load blocks may include resistor blocks, and the resistor blocks may include first blocks and second blocks. The first blocks are connected in series and have a first end connected to a voltage source and a second end connected to the oscillator unit. The second blocks are connected in series and have a first end connected to a ground and a second end connected to the oscillator unit. The first blocks and the second blocks are preferably symmetrical relative to each other.
The load blocks include connections therebetween. The connections may include fuse structures for enabling and disabling the load blocks to selectively connect the load blocks to the oscillator unit. The connections may include transistors for enabling and disabling the load blocks to selectively connect the load blocks to the oscillator unit. The load blocks may include a capacitor block having at least one capacitor element which is selectively connectable to the oscillator unit to further adjust the one of a plurality of clock frequencies. The load blocks may include a plurality of groups of capacitance elements, the groups of capacitance elements providing a plurality of levels of of the one of a plurality of clock frequencies. The plurality of load blocks may include programmable connections.
A universal clock generator circuit layout, in accordance with the present invention includes an oscillator circuit for providing a first clock frequency, and a plurality of resistor blocks including resistive elements. The resistor blocks including a first group of resistor blocks and a second group of resistor blocks. The first group of resistor blocks are connected in series and have a first end connected to a source and a second end connected to the oscillator circuit. The second group of resistor blocks are connected in series and have a first end connected to a ground and a second end connected to the oscillator circuit. A capacitor block has at least one capacitor element connected to the oscillator circuit. The plurality of resistor blocks and the capacitor block include selective connections which are enabled and disabled to adjust the first clock frequency by selectively connecting a number of the resistor blocks and capacitor elements to the oscillator unit to provide one of a plurality of clock frequencies from a same output.
In alternate embodiments, the resistor blocks may include a plurality of different resistance values for levels of adjustment of the one of a plurality of clock frequencies. The first blocks and the second blocks are preferably symmetrical relative to each other. The selective connections may include fuse structures for enabling and disabling the resistor blocks and the capacitive elements to selectively connect the resistor blocks and the capacitive elements to the oscillator circuit. The selective connections may include transistors for enabling and disabling the resistor blocks and the capacitive elements to selectively connect the resistor blocks and the capacitive elements to the oscillator circuit. The plurality of resistor blocks may include programmable connections. The layout is employed at a plurality of locations on a chip to provide different clock frequencies. The layout is the only type of clock circuit employed on a chip to provide different clock frequencies at a plurality of locations on the chip.
A method for providing clock signals on a chip, in accordance with the present invention, includes the step of providing a universal clock generator circuit comprising an oscillator unit including circuitry for providing a first clock frequency, and a plurality of load blocks, the load blocks being selectively connectable to the oscillator such that a range of clock rates are derived from the first clock frequency by selectively connecting a number of the load blocks to the oscillator unit to provide one of a plurality of clock frequencies from a same output. The method further includes the steps of placing the universal clock generator circuit at a plurality of locations on a semiconductor chip and trimming the load blocks to provide a clock frequency from each universal clock generator circuit on the semiconductor chip.
In other methods, the step of trimming the load blocks may include the step of providing connections and disconnections between the load blocks while forming the load blocks. The step of trimming the load blocks may include the step of providing connections and disconnections between the load blocks by respectively employing anti-fuses and fuses between the load blocks. The step of trimming the load blocks may include the step of providing connections and disconnections between the load blocks by employing transistors between the load blocks to enable and disable connections. The step of trimming the load blocks may include the step of eliminating load blocks from a layout to reduce layout area. The step of trimming the load blocks may also include the step of providing connections and disconnections between the load blocks by programming transistors between the load blocks to enable and disable connections. The step of programming transistors may include programming the transistors by employing a memory storage device. The transistors may be programmed after the semiconductor chip has been fabricated or packaged.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.